This application is a divisional of U.S. patent application Ser. No. 09/898,183, filed Jul. 3, 2001, now U.S. Pat. No. 6,714,050 which is a divisional application of U.S. patent application Ser. No. 09/535,064, filed Mar. 23, 2000, now U.S. Pat. No. 6,271,679 which claims the benefit of U.S. provisional patent application 60/126,235, filed Mar. 24, 1999, all of which are incorporated by reference herein, along with all of the references cited in these patent applications.
The present invention relates to the field of integrated circuits and more specifically, to output buffer circuitry capable of operating at the output voltage levels needed for a particular application.
As semiconductor processing technology continues to advance, integrated circuits or xe2x80x9cchipsxe2x80x9d continue to provide greater functionality and performance. Examples of some integrated circuits include microprocessors, application specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), and memories such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and nonvolatile memories (Flash and EEPROM). The positive power supply voltage used for integrated circuits of different process technologies is often different. Generally, newer process technologies use reduced positive power supply voltages. For example, previous generation integrated circuit used a supply voltage, VDD or VCC, or 5 volts. More recent integrated circuits used 3.3- and 3-volt power supplies. Some current integrated circuits use 2.5-volt power supplies. In the future, it is expected supply voltages will be further reduced to 2 volts and lower. Some of the expected power supply voltages will be 1.2 volts, 1 volt, and 0.8 volts. Therefore, each generation of integrated circuits is compatible with a particular power supply voltage and input and output standard.
In an electronic system, it is often desirable that an integrated circuit compatible with one input-output standard can be used with integrated circuits of other input-output standards. Among the many advantages of having such a chip, the integrated circuit customer can used that particular chip on a system board with chips of other input-output standards. The integrated circuit manufacturer can produce one chip that is compatible with current and previous generation technology.
Furthermore, when there are emerging I/O standards for integrated circuits such as for a low voltage TTL (LVTTL) output or low voltage differential signal (LVDS) output, the different standards often have different voltages for VOH and VOL. Until a uniform standard is adapted, it is desirable for integrated circuit makers to design their products to be compatible with as many of the standards as possible. This will increase the overall potential market for a particular product.
Therefore, there is a need for an output circuitry that is adaptable or configurable to different I/O standards.
The present invention provides circuitry to individually configure each I/O of an integrated circuit to different LVTTL I/O standards. This is done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The invention operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.
In an embodiment, the present invention is a programmable logic integrated circuit including a group of first I/O circuits connected to a supply voltage and a first configurable reference voltage. There is also a group of second I/O circuits connected to the supply voltage and a second configurable reference voltage. The first configurable reference voltage is different from the second configurable reference voltage. The group of first I/O circuits is compatible with a first I/O voltage standard based on the first configurable reference voltage and the group of second I/O circuits compatible with a second I/O voltage standard based on the second configurable reference voltage.
In one implementation, each I/O circuit includes a-first transistor connected between the supply voltage and a first node with a control electrode connected to a voltage level equal to the first reference voltage plus a threshold voltage of the first transistor. The circuitry includes a second transistor connected between the first node and a pad and a third transistor connected between the pad and ground. In a specific circuit implementation, the first transistor is NMOS, the second transistor in PMOS, and the first transistor is at least about ten times larger in size than the second transistor. In other implementation, the first transistor may be less than ten times larger than the second transistor.
In another implementation, each I/O circuit includes a first transistor connected between the supply voltage and a pad. A second transistor is connected between the pad and ground. A logic gate has an output connected to a control electrode of the first transistor. And, a differential amplifier circuit has a first input connected to the pad and a second input connected to the second reference voltage. The differential amplifier provides an output to an input of the logic gate, where the output is a logic high when a voltage at the second input is higher than a voltage at the first input and the output is a logic low when the voltage at the first input is higher than the voltage at the second input.
In another embodiment, the invention is a method of operating a programmable logic integrated circuit. A first reference voltage level is programmably selected to be connected to a first I/O circuit to select a first I/O standard the first I/O circuit will be compatible with. A second reference voltage level is programmably selected to be connected to a second I/O circuit to select a second I/O standard the second I/O circuit will be compatible with.
In another embodiment, the invention is an integrated circuit including a first transistor connected between a supply voltage and a first node, where a control electrode of the first transistor is connected to a reference voltage. A second transistor is connected between the first node and an output pad of the integrated circuit, where a voltage output high level at the pad will be the lesser of the reference voltage level or the supply voltage.
In another embodiment, the invention is an integrated circuit including a differential amplifier having a first input connected to a pad of the integrated circuit and a second input connected to a reference voltage. A pull-up transistor is connected between a supply voltage and the pad. And a logic gate having an output connected to a control electrode of the pull-up transistor and an input is connected to an output of the differential amplifier.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.